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Huawei's Tau Law: The Future of Chips?
29 May
Summary
- Huawei proposes Tau Scaling Law, focusing on signal delay reduction.
- LogicFolding architecture uses 3D stacking to shorten circuit pathways.
- Kirin chips in autumn 2026 will feature this new LogicFolding architecture.
Moore's Law, the long-standing principle of doubling transistors every two years, is facing significant physical and economic limitations. As global geometric scaling slows, major industry players are seeking new advancements.
Huawei has introduced a potential successor, the "Tau (τ) Scaling Law," focusing on reducing signal propagation delay. This new framework, nicknamed "Her's Law" by colleagues, prioritizes compressing the time constant τ.
The core innovation is the "LogicFolding" architecture. Instead of traditional 2D layouts, it employs a layered 3D approach, vertically stacking circuits. This drastically shortens critical-path wiring, reducing signal delays and improving performance.
Huawei reports mass production of 381 chips using this law. The Kirin chips, expected in autumn 2026, will be the first to adopt LogicFolding. By 2031, they anticipate high-end designs reaching 1.4 nm process equivalence.
While Huawei emphasizes collaboration, their claims await independent verification from competing firms. The industry watches to see if the Tau Scaling Law can genuinely propel semiconductor evolution beyond Moore's Law.
