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AMD's Venice Chip Powers Next-Gen AI on TSMC's 2nm
1 Jun
Summary
- AMD's Venice EPYC processor uses TSMC's advanced 2nm process.
- Venice is the first HPC product on TSMC's 2nm technology.
- AMD plans to expand 2nm production to Arizona facilities.
Advanced Micro Devices Inc. is making significant strides in its data center CPU roadmap with the commencement of production for its next-generation EPYC processor, codenamed Venice. This cutting-edge processor is being manufactured using Taiwan Semiconductor Manufacturing Company's (TSMC) advanced 2nm process technology, a move that AMD has hailed as an industry first for high-performance computing products.
The production ramp for the Venice processor is currently underway in Taiwan. However, AMD has indicated its intention to broaden this manufacturing capacity by expanding operations at TSMC's facility located in Arizona. This expansion signifies a strategic step towards enhancing global supply chain resilience and meeting the burgeoning demand for advanced computing solutions.
Furthermore, AMD is set to extend the application of TSMC's 2nm process technology across its broader data center CPU portfolio. This includes a subsequent EPYC processor, Verano, which will integrate LPDDR memory. This integration is crucial for delivering the enhanced CPU performance, energy efficiency, and bandwidth necessary to support the accelerating compute demands of artificial intelligence workloads.
